1. Field of the Invention
The present invention relates to a semiconductor device having a stacked structure in which a plurality of base materials are stacked in multiple layers and more particularly to a semiconductor device in which a plurality of wirings provided on each base material are connected to one another between respective adjacent base materials.
2. Description of the Related Art
In recent years, demands for intensified density (higher integration) and reduced size in the semiconductor device have been rising. To realize this, technologies for stacking a plurality of the base materials (substrates) in multiple layers have been developed. In such technologies, a mounting method for stacking a plurality of substrates each loaded with a semiconductor chip three-dimensionally in the thickness direction thereof and mounting these substrates on a single mother substrate has been proposed.
A plurality of wirings are provided on both front and rear major surfaces of a substrate (core layer, core substrate) for a general stacked structure. Each wiring has at least a connection terminal called land. Each land provided on one major surface of each substrate (wiring board) and each land provided on the other major surface are connected to each other through a via plug (via wiring) provided inside each wiring board. Usually, when respective wiring boards are stacked and bonded to each other, the lands opposing each other along the stacking direction are connected so that the respective wirings of the respective wiring boards are connected between adjacent wiring boards.
When respective wiring boards having such a structure are bonded to each other by stacking them, usually, the positions of the respective wiring boards in the vertical direction are aligned using a positioning pin or the like prior to bonding work so that lands of the respective wiring boards are connected as an appropriate pair (conduction passage) determined preliminarily. However, usually, the wiring pattern of each wiring differs depending on each wiring board or each major surface. Then, a displacement originated from a difference in wiring pattern always exists between the respective wirings opposing each other between upper and lower layers. That is, a so-called scale factor difference always exists between the respective wirings opposing each other between the upper and lower layers. Generally, a drilling accuracy of drilling a hole through which a positioning pin is to be passed in each wiring board and a clearance between the hole for the positioning pin provided in each wiring board and the positioning pin and the like are different depending on each wiring board. The displacement is always generated between the respective lands opposing each other or adjacent respective wiring boards due to these reasons.
If such a displacement exits, the likelihood that lands provided on major surfaces opposing each other of adjacent wiring boards may make contact with each other although they must not be connected to each other thereby causing a short-circuit is increased. Alternatively, the likelihood that a land provided on one major surface of the respective major surfaces opposing each other may not make contact with any land provided on the other major surface is increased. If a displacement occurs between lands opposing each other or wiring boards adjacent to each other, contact failure (conduction failure) of wirings between the respective wiring boards is likely to occur. As a result, the likelihood that the performance, quality, reliability and yield of the entire semiconductor device may drop is increased. Finally, the likelihood that production efficiency of the semiconductor device may drop thereby increasing production cost is increased.
To prevent such a problem, for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-57276 has disclosed a method for increasing the diameter of each land. According to this method, naturally, an allowance (allowable error) of displacement between the opposing lands and allowance of displacement of the stacking position between the stacked wiring substrates can be relaxed. However, in this method, an interval (connecting pitch) between respective lands provided adjacent to each other on the same major surface increases. Naturally, the connecting pitch between the lands on a mating to be connected to such a large diameter land also increases. Therefore, demands for intensifying the density and reducing the size of the semiconductor device are extremely difficult to achieve with this method.